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ltc2207/ltc2206 1 22076fa features descriptio u typical applicatio u applicatio s u 16-bit, 105msps/80msps adcs the ltc ? 2207/ltc2206 are 105msps/80msps, sampling 16-bit a/d converters designed for digitizing high fre- quency, wide dynamic range signals up to input frequencies of 700mhz. the input range of the adc can be optimized with the pga front end. the ltc2207/ltc2206 are perfect for demanding commu- nications applications, with ac performance that includes 78.2db noise floor and 100db spurious free dynamic range (sfdr). ultralow jitter of 80fs rms allows undersampling of high input frequencies with excellent noise performance. maximum dc specs include 4lsb inl, 1lsb dnl (no missing codes) over temperature. a separate output power supply allows the cmos output swing to range from 0.5v to 3.6v. the enc + and enc C inputs may be driven differentially or single-ended with a sine wave, pecl, lvds, ttl or cmos inputs. an optional clock duty cycle stabilizer al- lows high performance at full speed with a wide range of clock duty cycles. telecommunications receivers cellular base stations spectrum analysis imaging systems ate sample rate: 105msps/80msps 78.2dbfs noise floor 100db sfdr sfdr >82db at 250mhz (1.5v p-p input range) pga front end (2.25v p-p or 1.5v p-p input range) 700mhz full power bandwidth s/h optional internal dither optional data output randomizer single 3.3v supply power dissipation: 900mw/725mw optional clock duty cycle stabilizer out-of-range indicator pin compatible family 105msps: ltc2207 (16-bit), ltc2207-14 (14-bit) 80msps: ltc2206 (16-bit), ltc2206-14 (14-bit) 65msps: ltc2205 (16-bit), ltc2205-14 (14-bit) 40msps: ltc2204 (16-bit) 25msps: ltc2203 (16-bit) single-ended clock 10msps: ltc2202 (16-bit) single-ended clock 48-pin 7mm 7mm qfn package ? + s/h amp correction logic and shift register output drivers 16-bit pipelined adc core internal adc reference generator 1.25v common mode bias voltage clock/duty cycle control d15 d0 enc + pga shdn dith mode oe rand enc ? v cm analog input 22054 ta01 0.5v to 3.6v 3.3v 3.3v sense ognd ov dd 2.2 f 0.1 f 0.1 f 0.1 f 0.1 f v dd gnd adc control inputs ain + ain ? of clkout + clkout ? , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. patents pending. frequency (mhz) 0 amplitude (dbfs) ?70 ?30 0 40 22076 g05 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 10 20 30 50 ltc2207: 64k point fft, f in = 14.8mhz, C1dbfs, pga = 0, 105msps
ltc2207/ltc2206 2 22076fa converter characteristics package/order information absolute maximum ratings parameter conditions min typ max units integral linearity error differential analog input (note 5) t a = 25c 1.2 4 lsb integral linearity error differential analog input (note 5) 1.5 4.5 lsb differential linearity error differential analog input 0.3 1 lsb offset error (note 6) 1 8.5 mv offset drift 10 v/ c gain error external reference 0.2 1.5 %fs full-scale drift internal reference 30 ppm/c external reference 15 ppm/c transition noise 2.8 lsb rms supply voltage (v dd ) ................................... C0.3v to 4v digital output ground voltage (ognd) ........ C0.3v to 1v analog input voltage (note 3) ......C0.3v to (v dd + 0.3v) digital input voltage .....................C0.3v to (v dd + 0.3v) digital output voltage ................ C0.3v to (ov dd + 0.3v) power dissipation ............................................ 2000mw operating temperature range ltc2207c/ltc2206c ............................... 0c to 70c ltc2207i/ltc2206i ............................. C40c to 85c storage temperature range .................. C65c to 150c digital output supply voltage (ov dd ) .......... C0.3v to 4v ov dd = v dd (notes 1, 2) the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) top view uk package 48-lead (7mm 7mm) plastic qfn sense 1 v cm 2 v dd 3 v dd 4 gnd 5 ain + 6 ain ? 7 gnd 8 enc + 9 enc ? 10 gnd 11 v dd 12 36 ov dd 35 d11 34 d10 33 d9 32 d8 31 ognd 30 clkout + 29 clkout ? 28 d7 27 d6 26 d5 25 ov dd 48 gnd 47 pga 46 rand 45 mode 44 oe 43 of 42 d15 41 d14 40 d13 39 d12 38 ognd 37 ov dd v dd 13 v dd 14 gnd 15 shdn 16 dith 17 d0 18 d1 19 d2 20 d3 21 d4 22 ognd 23 ov dd 24 49 exposed pad is gnd (pin 49) must be soldered to pcb board t jmax = 150c, ja = 29c/w order part number uk part marking* ltc2207cuk ltc2206cuk ltc2207iuk ltc2206iuk ltc2207uk ltc2206uk ltc2207uk ltc2206uk order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ consult factory for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container.
ltc2207/ltc2206 3 22076fa the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C 1dbfs. (note 4) the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 3.135v v dd 3.465v 1.5 to 2.25 v p-p v in, cm analog input common mode differential input (note 7) 1 1.25 1.5 v i in analog input leakage current 0v a in + , a in C v dd (note 10) C1 1 a i sense sense input leakage current 0v sense v dd (note 11) C3 3 a i mode mode pin pull-down current to gnd 10 a c in analog input capacitance sample mode enc + < enc C 6.7 pf hold mode enc + > enc C 1.8 pf t ap sample-and-hold 1 ns acquisition delay time t jitter sample-and-hold 80 fs rms acquisition delay time jitter cmrr analog input 1v < (a in + = a in C ) <1.5v 80 db common mode rejection ratio bw-3db full power bandwidth r s 25 700 mhz symbol parameter conditions min ltc2206 typ max min ltc2207 typ max units snr signal-to-noise ratio 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 77.9 75.5 77.9 75.5 dbfs dbfs 15mhz input (2.25v range, pga = 0), 15mhz input (2.25v range, pga = 0) 15mhz input (1.5v range, pga = 1) 76.5 76.2 77.8 77.5 75.4 76.5 76.2 77.8 77.5 75.4 dbfs dbfs dbfs 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1) 77.5 75.3 77.5 75.3 dbfs dbfs 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1), 140mhz input (1.5v range, pga = 1) 73.8 73.4 76.7 74.8 74.5 73.8 73.4 76.7 74.8 74.5 dbfs dbfs dbfs 170mhz input (2.25v range, pga = 0) 170mhz input (1.5v range, pga = 1) 76.2 75.4 76.2 75.4 dbfs dbfs sfdr spurious free dynamic range 2 nd or 3 rd harmonic 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 100 100 100 100 dbc dbc 15mhz input (2.25v range, pga = 0), 15mhz input (2.25v range, pga = 0) 15mhz input (1.5v range, pga = 1) 87 86 95 95 100 88 87 95 95 100 dbc dbc dbc 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1) 90 95 90 95 dbc dbc 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1), 140mhz input (1.5v range, pga = 1) 84 83 85 90 89 84 83 85 90 89 dbc dbc dbc 170mhz input (2.25v range, pga = 0) 170mhz input (1.5v range, pga = 1) 82 86 82 86 dbc dbc dynamic accuracy analog input
ltc2207/ltc2206 4 22076fa the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C1dbfs unless otherwise noted. (note 4) symbol parameter conditions min ltc2206 typ max min ltc2207 typ max units sfdr spurious free dynamic range 4 th harmonic or higher 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 100 100 100 100 dbc dbc 15mhz input (2.25v range, pga = 0) 15mhz input (1.5v range, pga = 1) 90 100 100 90 100 100 dbc dbc 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1) 100 100 100 100 dbc dbc 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1) 88 95 100 88 95 100 dbc dbc 170mhz input (2.25v range, pga = 0) 170mhz input (1.5v range, pga = 1) 90 95 90 95 dbc dbc s/(n+d) signal-to-noise plus distortion ratio 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 77.9 75.5 77.9 75.5 dbfs dbfs 15mhz input (2.25v range, pga = 0) 15mhz input (2.25v range, pga = 0 15mhz input (1.5v range, pga = 1) 76.3 75.9 77.8 77.4 75.4 76.3 75.9 77.8 77.4 75.4 dbfs dbfs dbfs 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1) 77.1 75.2 77.1 75.2 dbfs dbfs 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1) 140mhz input (1.5v range, pga = 1) 73.6 73.2 75.6 74.6 74.3 73.6 73.2 75.6 74.6 74.3 dbfs dbfs dbfs 170mhz input (2.25v range, pga = 0) 170mhz input (1.5v range, pga = 1) 74.4 73.9 74.4 73.9 dbfs dbfs sfdr spurious free dynamic range at C25dbfs dither off 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 105 105 105 105 dbfs dbfs 15mhz input (2.25v range, pga = 0) 15mhz input (1.5v range, pga = 1) 105 105 105 105 dbfs dbfs 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1) 105 105 105 105 dbfs dbfs 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1) 100 100 100 100 dbfs dbfs 170mhz input (2.25v range, pga = 0) 170mhz input (1.5v range, pga = 1) 100 100 100 100 dbfs dbfs sfdr spurious free dynamic range at C25dbfs dither on 5mhz input (2.25v range, pga = 0) 5mhz input (1.5v range, pga = 1) 115 115 115 115 dbfs dbfs 15mhz input (2.25v range, pga = 0) 15mhz input (1.5v range, pga = 1) 100 115 115 100 115 115 dbfs dbfs 70mhz input (2.25v range, pga = 0) 70mhz input (1.5v range, pga = 1) 115 115 115 115 dbfs dbfs 140mhz input (2.25v range, pga = 0) 140mhz input (1.5v range, pga = 1) 110 110 110 110 dbfs dbfs 170mhz input (2.25v range, pga = 0) 170mhz input (1.5v range, pga = 1) 105 105 105 105 dbfs dbfs dynamic accuracy
ltc2207/ltc2206 5 22076fa parameter conditions min typ max units v cm output voltage i out = 0 1.15 1.25 1.35 v v cm output tempco i out = 0 40 ppm/c v cm line regulation 3.135v v dd 3.465v 1 mv/ v v cm output resistance C1ma | i out | 1ma 2 the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units encode inputs (enc + , enc C ) v id differential input voltage (note 7) 0.2 v v icm common mode input voltage internally set 1.6 v externally set (note 7) 1.4 3.0 r in input resistance (see figure 2) 6 k c in input capacitance (note 7) 3 pf logic inputs (dith, pga, shdn, rand) v ih high level input voltage v dd = 3.3v 2 v v il low level input voltage v dd = 3.3v 0.8 v i in input current v in = 0v to v dd 10 a c in input capacitance (note 7) 1.5 pf logic outputs ov dd = 3.3v v oh high level output voltage v dd = 3.3v i o = C10a 3.299 v i o = C200a 3.1 3.29 v v ol low level output voltage v dd = 3.3v i o = 160a 0.01 v i o = 1.6ma 0.10 0.4 v i source output source current v out = 0v C50 ma i sink output sink current v out = 3.3v 50 ma ov dd = 2.5v v oh high level output voltage v dd = 3.3v i o = C200a 2.49 v v ol low level output voltage v dd = 3.3v i o = 1.60ma 0.1 v ov dd = 1.8v v oh high level output voltage v dd = 3.3v i o = C200a 1.79 v v ol low level output voltage v dd = 3.3v i o = 1.60ma 0.1 v the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C1dbfs. (note 4) symbol parameter conditions min ltc2206 typ max min ltc2207 typ max units v dd analog supply voltage 3.135 3.3 3.465 3.135 3.3 3.465 v p shdn shutdown power shdn = v dd 0.2 0.2 mw ov dd output supply voltage 0.5 3.6 0.5 3.6 v i vdd analog supply current dc input 220 265 273 325 ma p dis power dissipation dc input 725 875 900 1,073 mw common mode bias characteristics digital inputs and digital outputs power requirements
ltc2207/ltc2206 6 22076fa t h t d t c t l n ? 7 n ? 6 n ? 5 n ? 4 n ? 3 analog input enc ? enc + clkout ? clkout + d0-d15, of 22076 td01 t ap n + 1 n + 2 n + 4 n + 3 n timing diagram note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd, with gnd and ognd shorted (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: v dd = 3.3v, f sample = 105mhz (ltc2207), 80mhz (ltc2206) differential enc + /enc C = 2v p-p sine wave with 1.6v common mode, input range = 2.25v p-p with differential drive (pga = 0), unless otherwise speci? ed. note 5: integral nonlinearity is de? ned as the deviation of a code from a best ? t straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 6: offset error is the offset voltage measured from C1/2lsb when the output code ? ickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2s complement output mode. note 7: guaranteed by design, not subject to test. note 8: v dd = 3.3v, f sample = 105mhz (ltc2207) or 80mhz (ltc2206), input range = 2.25v p-p with differential drive. note 9: recommended operating conditions. note 10: the dynamic current of the switched capacitors analog inputs can be large compared to the leakage current and will vary with the sample rate. note 11: leakage current will have higher transient current at power up. keep drive resistance at or below 1kohm. the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min ltc2206 typ max min ltc2207 typ max units f s sampling frequency (note 9) 1 80 1 105 mhz t l enc low time duty cycle stabilizer off (note 7) duty cycle stabilizer on (note 7) 5.94 4.06 6.25 6.25 500 500 4.52 3.10 4.762 4.762 500 500 ns ns t h enc high time duty cycle stabilizer off (note 7) duty cycle stabilizer on (note 7) 5.94 4.06 6.25 6.25 500 500 4.52 3.10 4.762 4.762 500 500 ns ns t ap sample-and-hold aperture delay C0.7 C0.7 ns t d enc to data delay (note 7) 1.3 2.7 4 1.3 2.7 4 ns t c enc to clkout delay (note 7) 1.3 2.7 4 1.3 2.7 4 ns t skew data to clkout skew (t c -t d ) (note 7) C0.6 0 0.6 C0.6 0 0.6 ns t oe data access time bus relinquish time cl = 5pf (note 7) (note 7) 5 5 15 15 5 5 15 15 ns ns pipeline latency 7 7 cycles timing characteristics
ltc2207/ltc2206 7 22076fa output code 0 inl error (lsb) 0 1.0 65536 22076 g01 ?1.0 ?2.0 16384 32768 49152 8192 24576 40960 57344 2.0 ?0.5 0.5 ?1.5 1.5 output code 0 ?1.0 inl error (lsb) ?0.8 ?0.4 ?0.2 0 1.0 0.4 16384 32768 40960 22076 g02 ?0.6 0.6 0.8 0.2 8192 24576 49152 57344 6553 6 output code count 6000 8000 9000 7000 5000 3000 1000 10000 32811 22076 g03 4000 2000 0 32803 32801 32805 32807 32809 32815 32817 32819 32821 32813 32823 frequency (mhz) 0 amplitude (dbfs) ?70 ?30 0 40 22076 g04 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 10 20 30 50 frequency (mhz) 0 amplitude (dbfs) ?70 ?30 0 40 22076 g05 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 10 20 30 50 frequency (mhz) 0 amplitude (dbfs) ?70 ?30 0 40 22076 g06 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 10 20 30 50 input level (dbfs) ?80 0 sfdr (dbc and dbfs) 20 40 60 140 100 ?60 ?40 ?30 120 80 ?70 ?50 -20 ?10 0 22076 g07 input level (dbfs) ?80 0 sfdr (dbc and dbfs) 20 40 60 140 100 ?60 ?40 ?30 120 80 ?70 ?50 -20 ?10 0 22076 g08 frequency (mhz) 0 amplitude (dbfs) ?70 ?30 0 40 22076 g09 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 10 20 30 50 ltc2207: dnl, 105msps ltc2207: ac grounded input histogram, 105msps ltc2207: 128k point fft, f in = 4.93mhz, C1dbfs, pga = 0, 105msps ltc2207: 64k point fft, f in = 14.8mhz, C1dbfs, pga = 0, 105msps ltc2207: 64k point fft, f in = 14.8mhz, C10dbfs, pga = 0, 105msps ltc2207: sfdr vs input level, f in = 15mhz, pga = 0, dither on, 105msps ltc2207: 64k point 2-tone fft, f in = 14.8mhz and 18.6mhz, C7dbfs, pga = 0, 105msps ltc2207: inl, 105msps ltc2207: sfdr vs input level, f in = 15mhz, pga = 0, dither off, 105msps typical performance characteristics
ltc2207/ltc2206 8 22076fa frequency (mhz) 0 amplitude (dbfs) ?70 ?30 0 40 22076 g10 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 10 20 30 50 frequency (mhz) 0 amplitude (dbfs) ?70 ?30 0 40 22076 g11 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 10 20 30 50 frequency (mhz) 0 amplitude (dbfs) ?70 ?30 0 40 22076 g12 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 10 20 30 50 frequency (mhz) 0 amplitude (dbfs) ?70 ?30 0 40 22076 g13 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 10 20 30 50 frequency (mhz) 0 amplitude (dbfs) ?70 ?30 0 40 22076 g14 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 10 20 30 50 frequency (mhz) 0 amplitude (dbfs) ?70 ?30 0 40 22076 g15 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 10 20 30 50 input level (dbfs) ?70 0 sfdr (dbc and dbfs) 20 40 60 70 50 30 10 140 130 110 100 ?60 ?40 ?30 0 120 80 90 ?50 ?20 ?10 22076 g16 input level (dbfs) ?70 0 sfdr (dbc and dbfs) 20 40 60 70 50 30 10 140 130 110 100 ?60 ?40 ?30 0 120 80 90 ?50 ?20 ?10 22076 g17 frequency (mhz) 0 amplitude (dbfs) ?70 ?30 0 40 22076 g18 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 10 20 30 50 ltc2207: 64k point 2-tone fft, f in = 14.8mhz and 18.6mhz, C15dbfs, pga = 0, 105msps ltc2207: 64k fft, f in = 70.1mhz, C1dbfs, pga = 0, 105msps ltc2207: 64k point fft, f in = 70.1mhz, C1dbfs, pga = 1, 105msps ltc2207: 128k point fft, f in = 70.1mhz, C20dbfs, pga = 0, 105msps ltc2207: 128k point fft, f in = 70.1mhz, C20dbfs, pga = 0, dither on, 105msps ltc2207: 64k point fft, f in = 140.2mhz, C1dbfs, pga = 1, 105msps ltc2207: sfdr vs input level, f in = 140mhz, pga = 1, dither off, 105msps ltc2207: sfdr vs input level, f in = 140mhz, pga = 1, dither on, 105msps ltc2207: 64k point fft, f in = 170.2mhz, C1dbfs, pga = 0, 105msps typical performance characteristics
ltc2207/ltc2206 9 22076fa frequency (mhz) 0 amplitude (dbfs) ?70 ?30 0 40 22076 g19 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 10 20 30 50 input frequency (mhz) 0 sfdr (dbc) 80 85 90 300 500 22076 g20 75 70 65 100 200 400 95 100 105 pga = 0 pga = 1 input frequency (mhz) 0 snr (dbfs) 73 74 75 300 500 22076 g21 72 71 70 100 200 400 76 77 78 pga = 0 pga = 1 sample rate (msps) 0 90 95 105 75 125 22076 g22 85 80 25 50 100 150 175 75 70 100 snr and sfdr (dbfs) limit sfdr snr supply voltage (v) 2.8 snr and sfdr (dbfs) 90 95 100 3.4 22076 g23 85 80 70 3 3.2 75 110 105 sfdr snr upper limit lower limit duty cycle (%) 30 sfdr and snr (dbfs) 80 90 70 22076 g24 70 60 40 50 60 110 100 snr dcs off snr dcs on sfdr dcs off sfdr dcs on sample rate (msps) 0 200 ivdd (ma) 220 230 240 250 260 270 50 100 22076 g25 280 290 300 210 150 ltc2207: 64k point fft, f in = 250.2mhz, C1dbfs, pga = 0, 105msps ltc2207: sfdr (hd2 and hd3) vs input frequency, 105msps ltc2207: snr vs input frequency, 105msps ltc2207: 5mhz snr and sfdr vs sample rate, 105msps ltc2207: snr and sfdr vs supply voltage (vdd), f in = 5mhz, 105msps ltc2207: snr and sfdr vs duty cycle, 105msps ltc2207: ivdd vs sample rate, 5mhz sine wave, C1dbfs, 105msps typical performance characteristics
ltc2207/ltc2206 10 22076fa output code 0 inl error (lsb) 0 1.0 65536 22076 g26 ?1.0 ?2.0 16384 32768 49152 8192 24576 40960 57344 2.0 ?0.5 0.5 ?1.5 1.5 output code 0 ?1.0 inl error (lsb) ?0.8 ?0.4 ?0.2 0 1.0 0.4 16384 32768 40960 22076 g27 ?0.6 0.6 0.8 0.2 8192 24576 49152 57344 6553 6 output code count 6000 8000 9000 7000 5000 3000 1000 10000 22076 g28 4000 2000 0 32821 32813 32811 32815 32817 32819 32825 32827 32829 32831 32823 32833 frequency (mhz) 0 amplitude (dbfs) ?70 ?30 0 20 22076 g29 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 5 10 15 40 35 30 25 frequency (mhz) 0 amplitude (dbfs) ?70 ?30 0 20 22076 g30 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 5 10 15 40 35 30 25 frequency (mhz) 0 amplitude (dbfs) ?70 ?30 0 20 22076 g31 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 5 10 15 40 35 30 25 frequency (mhz) 0 amplitude (dbfs) ?70 ?30 0 20 22076 g32 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 5 10 15 40 35 30 25 frequency (mhz) 0 amplitude (dbfs) ?70 ?30 0 20 22076 g33 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 5 10 15 40 35 30 25 input level (dbfs) ?70 sfdr (dbc and dbfs) 80 100 120 ?40 ?20 22076 g34 60 40 ?60 ?50 ?30 ?10 0 20 0 ltc2206: inl, 80msps ltc2206: dnl, 80msps ltc2206: 64k point ac grounded histogram, 80msps ltc2206: 128k point fft, f in = 4.93mhz, C1dbfs, pga = 0, 80msps ltc2206: 64k point fft, f in = 10.1mhz, C1dbfs, pga = 0, 80msps ltc2206: 128k point fft, f in = 10.1mhz, C20dbfs, pga = 0, dither off, 80msps ltc2206: 128k point fft, f in = 10.1mhz, C20dbfs, pga = 0, dither on, 80msps ltc2206: 64k point fft, f in = 15.1mhz, C1dbfs, pga = 0, 80msps ltc2206: sfdr vs input level, f in = 15mhz, pga = 0, 80msps typical performance characteristics
ltc2207/ltc2206 11 22076fa input level (dbfs) ?70 sfdr (dbc and dbfs) 80 100 140 120 ?40 ?20 22076 g35 60 40 ?60 ?50 ?30 ?10 0 20 0 frequency (mhz) 0 amplitude (dbfs) ?70 ?30 0 20 22076 g36 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 5 10 15 40 35 30 25 frequency (mhz) 0 amplitude (dbfs) ?70 ?30 0 20 22076 g37 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 5 10 15 40 35 30 25 frequency (mhz) 0 amplitude (dbfs) ?70 ?30 0 20 22076 g38 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 5 10 15 40 35 30 25 frequency (mhz) 0 amplitude (dbfs) ?70 ?30 0 20 22076 g39 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 5 10 15 40 35 30 25 frequency (mhz) 0 amplitude (dbfs) ?70 ?30 0 20 22076 g40 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 5 10 15 40 35 30 25 frequency (mhz) 0 amplitude (dbfs) ?70 ?30 0 20 22076 g41 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 5 10 15 40 35 30 25 frequency (mhz) 0 amplitude (dbfs) ?70 ?30 0 20 22076 g42 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 5 10 15 40 35 30 25 frequency (mhz) 0 amplitude (dbfs) ?70 ?30 0 20 22076 g43 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 5 10 15 40 35 30 25 ltc2206: sfdr vs input level f in = 15mhz, pga = 0, dither on, 80msps ltc2206: 64k point 2-tone fft, f in = 14.8mhz and 18.6mhz, C7dbfs, pga = 0, 80msps ltc2206: 64k point 2-tone fft, f in = 14.8mhz and 18.6mhz, C15dbfs, pga = 0, 80msps ltc2206: 64k point fft, f in = 25.1mhz, C1dbfs, pga = 0, 80msps ltc2206: 64k point fft, f in = 70.2mhz, C1dbfs, pga = 0, 80msps ltc2206: 64k point fft, f in = 70.2mhz, C1dbfs, pga = 1, 80msps ltc2206: 64k point 2-tone fft, f in = 69.2mhz and 76.5mhz, C7dbfs, pga = 0, 80msps ltc2206: 64k point 2-tone fft, f in = 69.2mhz and 76.5mhz, C15dbfs, pga = 0, 80msps ltc2206: 64k point fft, f in = 140.2mhz, C1dbfs, pga = 0, 80msps typical performance characteristics
ltc2207/ltc2206 12 22076fa input level (dbfs) ?80 30 sfdr (dbc and dbfs) 40 60 70 80 130 100 ?60 ?40 ?30 22076 g44 50 110 120 90 ?70 ?50 ?20 ?10 0 input level (dbfs) ?80 30 sfdr (dbc and dbfs) 40 60 70 80 130 100 ?60 ?40 ?30 22076 g45 50 110 120 90 ?70 ?50 ?20 ?10 0 frequency (mhz) 0 amplitude (dbfs) ?70 ?30 0 20 22076 g46 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 5 10 15 40 35 30 25 frequency (mhz) 0 amplitude (dbfs) ?70 ?30 0 20 22076 g47 ?90 ?110 ?80 ?50 ?10 ?20 ?40 ?60 ?100 ?120 ?130 5 10 15 40 35 30 25 input frequency (mhz) 0 60 sfdr (dbc) 65 75 80 85 200 400 500 105 22076 g48 70 100 300 90 95 100 pga = 0 pga = 1 input frequency (mhz) 0 snr (dbfs) 75 77 79 400 22076 g49 73 71 74 76 78 72 70 69 100 200 300 500 pga = 0 pga = 1 sample rate (mhz) 0 sfdr and snr (dbrs) 90 95 100 120 140 100 22076 g50 85 80 40 20 80 60 160 75 70 105 sfdr snr limit supply voltage (v) 2.8 snr and sfdr (dbfs) 90 95 100 3.4 22076 g51 85 80 70 3 3.2 75 110 105 snr sfdr lower limit upper limit sample rate (msps) 0 ivdd (ma) 210 230 250 80 22076 g52 190 170 200 220 240 180 160 150 20 40 60 100 ltc2206: sfdr vs input level, f in = 140.2mhz, pga = 0, dither off, 80msps ltc2206: sfdr vs input level, f in = 140.2mhz, pga = 0, dither on, 80msps ltc2206: 64k point fft, f in = 170.2mhz, C1dbfs, pga = 1, 80msps ltc2206: 64k point fft, f in = 250.2mhz, C1dbfs, pga = 1, 80msps ltc2206: sfdr (hd2 and hd3) vs input frequency, 80msps ltc2206: snr vs input frequency, 80msps ltc2206: 5mhz sfdr and snr vs sample rate, 80msps ltc2206: snr and sfdr vs supply voltage (vdd), f in = 5mhz, 80msps ltc2206: ivdd vs sample rate, 5mhz sine wave, C1dbfs, 80msps typical performance characteristics
ltc2207/ltc2206 13 22076fa temperature ( c) ?40 offset voltage (mv) ?2 0 2 35 85 22076 g53 ?4 ?6 ?8 ?15 10 60 4 6 8 temperature ( c) ?40 0.995 normalized full-scale 0.996 0.997 0.998 0.999 1.000 1.001 ?15 10 35 60 22076 g54 85 analog input common mode voltage (v) 0.5 60 sfdr (dbfs) 70 80 90 0.75 1 1.25 1.5 22076 g55 1.75 100 110 65 75 85 95 105 2 70mhz 10mhz offset voltage vs temperature, internal reference, 5 units normalized full-scale error vs temperature, internal reference, 5 units sfdr vs analog input common mode voltage, 10mhz and 70mhz, C1dbfs, pga = 0 typical performance characteristics
ltc2207/ltc2206 14 22076fa sense (pin 1): reference mode select and external reference input. tie sense to v dd to select the internal 2.5v bandgap reference. an external reference of 2.5v or 1.25v may be used; both reference values will set a full scale adc range of 2.25v (pga = 0). v cm (pin 2): 1.25v output. optimum voltage for input com- mon mode. must be bypassed to ground with a minimum of 2.2f. ceramic chip capacitors are recommended. v dd (pins 3, 4, 12, 13, 14): 3.3v analog supply pin. bypass to gnd with 0.1f ceramic chip capacitors. gnd (pins 5, 8, 11, 15, 48, 49): adc power ground. a in + (pin 6): positive differential analog input. a in C (pin 7): negative differential analog input. enc + (pin 9): positive differential encode input. the sampled analog input is held on the rising edge of enc + . internally biased to 1.6v through a 6.2k resistor. output data can be latched on the rising edge of enc + . enc C (pin 10): negative differential encode input. the sampled analog input is held on the falling edge of enc C . internally biased to 1.6v through a 6.2k resistor. by- pass to ground with a 0.1f capacitor for a single-ended encode signal. shdn (pin 16): power shutdown pin. shdn = low results in normal operation. shdn = high results in powered down analog circuitry and the digital outputs are placed in a high impedance state. dith (pin 17): internal dither enable pin. dith = low disables internal dither. dith = high enables internal dither. refer to internal dither section of this data sheet for details on dither operation. d0-d15 (pins 18-22, 26-28, 32-35 and 39-42): digital outputs. d15 is the msb. ognd (pins 23, 31 and 38): output driver ground. ov dd (pins 24, 25, 36, 37): positive supply for the output drivers. bypass to ground with 0.1f capacitor. clkout C (pin 29): data valid output. clkout C will toggle at the sample rate. latch the data on the falling edge of clkout C . clkout + (pin 30): inverted data valid output. clkout + will toggle at the sample rate. latch the data on the rising edge of clkout + . of (pin 43): over/under flow digital output. of is high when an over or under ? ow has occurred. ?? o ? e (pin 44): output enable pin. low enables the digital output drivers. high puts digital outputs in hi-z state. mode (pin 45): output format and clock duty cycle stabilizer selection pin. connecting mode to 0v selects offset binary output format and disables the clock duty cycle stabilizer. connecting mode to 1/3v dd selects offset binary output format and enables the clock duty cycle sta- bilizer. connecting mode to 2/3v dd selects 2s complement output format and enables the clock duty cycle stabilizer. connecting mode to v dd selects 2s complement output format and disables the clock duty cycle stabilizer. rand (pin 46): digital output randomization selection pin. rand low results in normal operation. rand high selects d1-d15 to be exclusive-ored with d0 (the lsb). the output can be decoded by again applying an xor operation between the lsb and all other bits. this mode of operation reduces the effects of digital output interferance. pga (pin 47): programmable gain ampli? er control pin. low selects a front-end gain of 1, input range of 2.25v p-p . high selects a front-end gain of 1.5, input range of 1.5v p-p . gnd (exposed pad, pin 49): adc power ground. the ex- posed pad on the bottom of the package must be soldered to ground. pin functions
ltc2207/ltc2206 15 22076fa dith oe mode pga rand shdn adc clocks differential input low jitter clock driver dither signal generator first pipelined adc stage fifth pipelined adc stage fourth pipelined adc stage second pipelined adc stage enc + enc ? correction logic and shift register ognd clkout+ clkout? of d15 d14 ov dd d1 d0 22076 f01 input s/h a in ? a in + third pipelined adc stage output drivers control logic v dd gnd pga sense v cm buffer adc reference voltage reference range select figure 1. functional block diagram block diagram
ltc2207/ltc2206 16 22076fa dynamic performance signal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio [s/(n+d)] is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the adc output. the output is band lim- ited to frequencies above dc to below half the sampling frequency. signal-to-noise ratio the signal-to-noise (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components, except the ? rst ? ve harmonics. total harmonic distortion total harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd = C20log ( (v 2 2 + v 3 2 + v 4 2 + ... v n 2 )/v 1 ) where v 1 is the rms amplitude of the fundamental fre- quency and v 2 through v n are the amplitudes of the second through nth harmonics. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the adc input, nonlinearities in the adc transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. for example, the 3nd order imd terms include (2fa + fb), (fa + 2fb), (2fa - fb) and (fa - 2fb). the 3rd order imd is de? ned as the ration of the rms value of either input tone to the rms value of the largest 3rd order imd product. spurious free dynamic range (sfdr) the ratio of the rms input signal amplitude to the rms value of the peak spurious spectral component expressed in dbc. sfdr may also be calculated relative to full scale and expressed in dbfs. full power bandwidth the full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full scale input signal. aperture delay time the time from when a rising enc + equals the enc C voltage to the instant that the input signal is held by the sample- and-hold circuit. aperture delay jitter the variation in the aperture delay time from convertion to conversion. this random variation will result in noise when sampling an ac input. the signal to noise ratio due to the jitter alone will be: snr jitter = C20log (2 ? f in ? t jitter ) operation
ltc2207/ltc2206 17 22076fa converter operation the ltc2207/ltc2206 are cmos pipelined multistep con- verters with a front-end pga. as shown in figure 1, the con- verter has ? ve pipelined adc stages; a sampled analog input will result in a digitized value seven cycles clock later (see the timing diagram section). the analog input is differential for improved common mode noise immunity and to maximize the input range. additionally, the differential input drive will reduce even order harmonics of the sample and hold circuit. the encode input is also differential for improved common mode noise immunity. the ltc2207/ltc2206 have two phases of operation, determined by the state of the differential enc + /enc C input pins. for brevity, the text will refer to enc + great- er than enc C as enc high and enc + less than enc C as enc low. each pipelined stage shown in figure 1 contains an adc, a reconstruction dac and an interstage ampli? er. in operation, the adc quantizes the input to the stage and the quantized value is subtracted from the input by the dac to produce a residue. the residue is ampli? ed and output by the residue ampli? er. successive stages oper- ate out of phase so that when odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. when enc is low, the analog input is sampled differen- tially directly onto the input sample-and-hold capacitors, inside the input s/h shown in the block diagram. at the instant that enc transitions from low to high, the voltage on the sample capacitors is held. while enc is high, the held input voltage is buffered by the s/h ampli? er which drives the ? rst pipelined adc stage. the ? rst stage acquires the output of the s/h ampli? er during the high phase of enc. when enc goes back low, the ? rst stage produces its residue which is acquired by the second stage. at the same time, the input s/h goes back to acquiring the analog input. when enc goes high, the second stage produces its residue which is acquired by the third stage. an iden- tical process is repeated for the third and fourth stages, resulting in a fourth stage residue that is sent to the ? fth stage for ? nal evaluation. each adc stage following the ? rst has additional range to accommodate ? ash and ampli? er offset errors. results from all of the adc stages are digitally delayed such that the results can be properly combined in the correction logic before being sent to the output buffer. applications information
ltc2207/ltc2206 18 22076fa figure 2. equivalent input circuit c sample 4.9pf v dd v dd ltc2207/ltc2206 a in + 22076 f02 c sample 4.9pf v dd a in ? enc ? enc + 1.6v 6k 1.6v 6k c parasitic 1.8pf c parasitic 1.8pf sample/hold operation and input drive sample/hold operation figure 2 shows an equivalent circuit for the ltc2207/ ltc2206 cmos differential sample and hold. the differ- ential analog inputs are sampled directly onto sampling capacitors (c sample ) through nmos transitors. the capacitors shown attached to each input (c parasitic ) are the summation of all other capacitance associated with each input. during the sample phase when enc is low, the nmos transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. when enc transitions from low to high, the sampled input voltage is held on the sampling capacitors. during the hold phase when enc is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the adc core for processing. as enc transitions for high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. if the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. if the input change is large, such as the change seen with input frequencies near nyquist, then a larger charging glitch will be seen. common mode bias the adc sample-and-hold circuit requires differential drive to achieve speci? ed performance. each input should swing 0.5625v for the 2.25v range (pga = 0) or 0.375v for the 1.5v range (pga = 1), around a common mode voltage of 1.25v. the v cm output pin (pin 2) is designed to provide the common mode bias level. v cm can be tied directly to the center tap of a transformer to set the dc input level or as a reference level to an op amp differential driver circuit. the v cm pin must be bypassed to ground close to the adc with 2.2f or greater. input drive impedence as with all high performance, high speed adcs the dynamic performance of the ltc2207/ltc2206 can be in? uenced by the input drive circuitry, particularly the second and third harmonics. source impedance and in- put reactance can in? uence sfdr. at the falling edge of enc the sample-and-hold circuit will connect the 4.9pf sampling capacitor to the input pin and start the sampling period. the sampling period ends when enc rises, hold- ing the sampled input on the sampling capacitor. ideally, the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2f encode ); however, this is not always possible and the incomplete settling may degrade the sfdr. the sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. for the best performance it is recomended to have a source impedence of 100 or less for each input. the source impedence should be matched for the differential inputs. poor matching will result in higher even order harmonics, especially the second. applications information
ltc2207/ltc2206 19 22076fa input drive circuits input filtering a ? rst order rc lowpass ? lter at the input of the adc can serve two functions: limit the noise from input cir- cuitry and provide isolation from adc s/h switching. the ltc2207/ltc2206 have a very broadband s/h circuit, dc to 700mhz; it can be used in a wide range of applications; therefore, it is not possible to provide a single recom- mended rc ? lter. figures 3, 4a and 4b show three examples of input rc ? ltering at three ranges of input frequencies. in general it is desirable to make the capacitors as large as can be toleratedthis will help suppress random noise as well as noise coupled from the digital circuitry. the ltc2207/ ltc2206 do not require any input ? lter to achieve data sheet speci? cations; however, no ? ltering will put more stringent noise requirements on the input drive circuitry. transformer coupled circuits figure 3 shows the ltc2207/ltc2206 being driven by an rf transformer with a center-tapped secondary. the secondary center tap is dc biased with v cm , setting the adc input signal at its optimum dc level. figure 3 shows a 1:1 turns ratio transformer. other turns ratios can be used; however, as the turns ratio increases so does the impedance seen by the adc. source impedance greater than 50 can reduce the input bandwidth and increase 0.1 f a in + a in ? 4.7pf 2.2 f 4.7pf 4.7pf v cm ltc2207/ ltc2206 analog input 0.1 f 0.1 f t1 1:1 t1 = ma/com etc1-1-13 resistors, capacitors are 0402 package size except 2.2 f 22076 f04a 5 ? 10 ? 25 ? 25 ? 10 ? 5 ? figure 4a. using a transmission line balun transformer. recommended for input frequencies from 100mhz to 250mhz 0.1 f a in + a in ? 2.2 f 2.2pf 2.2pf v cm ltc2207/ ltc2206 analog input 0.1 f 0.1 f t1 1:1 t1 = ma/com etc1-1-13 resistors, capacitors are 0402 package size except 2.2 f 22076 f04b 5 ? 25 ? 25 ? 5 ? figure 4b. using a transmission line balun transformer. recommended for input frequencies from 250mhz to 500mhz high frequency distortion. a disadvantage of using a transformer is the loss of low frequency response. most small rf transformers have poor performance at frequen- cies below 1mhz. center-tapped transformers provide a convenient means of dc biasing the secondary; however, they often show poor balance at high input frequencies, resulting in large 2nd order harmonics. figure 4a shows transformer coupling using a transmis- sion line balun transformer. this type of transformer has much better high frequency response and balance than ? ux coupled center tap transformers. coupling capacitors are added at the ground and input primary terminals to allow the secondary terminals to be biased at 1.25v. figure 4b shows the same circuit with components suitable for higher input frequencies. figure 3. single-ended to differential conversion using a transformer. recommended for input frequencies from 5mhz to 150mhz 35 ? 5 ? 35 ? 10 ? 10 ? 5 ? 5 ? 0.1 f a in + a in ? 8.2pf 2.2 f 8.2pf 8.2pf v cm ltc2207/ ltc2206 t1 t1 = ma/com etc1-1t resistors, capacitors are 0402 package size except 2.2 f 22076 f03 applications information
ltc2207/ltc2206 20 22076fa figure 5. dc coupled input with differential ampli? er ? ? + + a in + a in ? 2.2 f 12pf 12pf v cm ltc2207/ ltc2206 analog input 22076 f05 cm amplifier = ltc6600-20, ltc1993, etc. high speed differential amplifier 25 ? 25 ? pga 1.25v sense v cm buffer internal adc reference range select and gain control 2.5v bandgap reference 2.2 f tie to v dd to use internal 2.5v reference or input for external 2.5v reference or input for external 1.25v reference 22076 f06 ltc2207/ ltc2206 figure 6. reference circuit direct coupled circuits figure 5 demonstrates the use of a differential ampli? er to convert a single ended input signal into a differential input signal. the advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of any op amp or closed-loop ampli? er will de- grade the adc sfdr at high input frequencies. additionally, wideband op amps or differential ampli? ers tend to have high noise. as a result, the snr will be degraded unless the noise bandwidth is limited prior to the adc input. reference operation figure 6 shows the ltc2207/ltc2206 reference circuitry consisting of a 2.5v bandgap reference, a programmable gain ampli? er and control circuit. the ltc2207/ltc2206 have three modes of reference operation: internal refer- ence, 1.25v external reference or 2.5v external reference. to use the internal reference, tie the sense pin to v dd . to use an external reference, simply apply either a 1.25v or 2.5v reference voltage to the sense input pin. both 1.25v and 2.5v applied to sense will result in a full scale range of 2.25v p-p (pga = 0). a 1.25v output v cm is provided for a common mode bias for input drive circuitry. an external bypass capacitor is required for the v cm output. this provides a high frequency low impedance path to ground for internal and external circuitry. this is also the compensation capacitor for the reference; it will not be stable without this capacitor. the minimum value required for stability is 2.2f. the internal programmable gain ampli? er provides the internal reference voltage for the adc. this ampli? er has very stringent settling requirements and is not accessible for external use. the sense pin can be driven 5% around the nominal 2.5v or 1.25v external reference inputs. this adjustment range can be used to trim the adc gain error or other system gain errors. when selecting the internal reference, the sense pin should be tied to v dd as close to the converter as possible. if the sense pin is driven externally it should be bypassed to ground as close to the device as possible with 1f (or larger) ceramic capacitor. pga pin the pga pin selects between two gain settings for the adc front-end. pga = 0 selects an input range of 2.25v p- p ; pga = 1 selects an input range of 1.5v p-p . the 2.25v input range has the best snr; however, the distortion will be higher for input frequencies above 100mhz. for ap- plications with high input frequencies, the low input range will have improved distortion; however, the snr will be 2.4db worse. see the typical performance characteristics section of this datasheet. applications information
ltc2207/ltc2206 21 22076fa 22076 f10 enc ? enc + 3.3v 3.3v d0 q0 q0 mc100lvelt22 ltc2207/ ltc2206 figure 10. enc drive using a cmos to pecl translator figure 9. single-ended enc drive, not recommended for low jitter 22076 f09 enc ? 1.6v v threshold = 1.6v enc + 0.1 f ltc2207/ ltc2206 figure 7. a 2.25v range adc with an external 2.5v reference v cm sense 1.25v 3.3v 2.2 f 2.2 f 1 f 22076 f07 ltc2207/ ltc2206 ltc1461-2.5 2 6 4 figure 8a. equivalent encode input circuit figure 8b. transformer driven encode v dd v dd ltc2207/ ltc2206 22076 f08a v dd enc ? enc + 1.6v 1.6v 6k 6k to internal adc clock drivers 50 ? 100 ? 8.2pf 0.1 f 0.1 f 0.1 f t1 t1 = ma/com etc1-1-13 resistors and capacitors are 0402 package size 50 ? ltc2207/ ltc2206 22076 f08b enc ? enc + applications information
ltc2207/ltc2206 22 22076fa maximum and minimum encode rates the maximum encode rate for the ltc2207 is 105msps. the maximum encode rate for the ltc2206 is 80msps. for the adc to operate properly the encode signal should have a 50% (5%) duty cycle. each half cycle must be at least 4.52ns for the ltc2207 internal circuitry to have enough settling time for proper operation. for the ltc2206, each half cycle must be at least 5.94ns. achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as pecl or lvds. when using a single-ended encode signal asymmetric rise and fall times can result in duty cycles that are far from 50%. an optional clock duty cycle stabilizer can be used if the input clock does not have a 50% duty cycle. this circuit uses the rising edge of enc pin to sample the analog input. the falling edge of enc is ignored and an internal falling edge is generated by a phase-locked loop. the input clock duty cycle can vary from 30% to 70% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the pll to lock onto the input clock. to use the clock duty cycle stabilizer, the mode pin must be connected to 1/3v dd or 2/3v dd using external resistors. the lower limit of the ltc2207/ltc2206 sample rate is determined by droop of the sample and hold circuits. the pipelined architecture of this adc relies on storing analog signals on small valued capacitors. junction leakage will discharge the capacitors. the speci? ed minimum operating frequency for the ltc2207/ltc2206 is 1msps. driving the encode inputs the noise performance of the ltc2207/ltc2206 can depend on the encode signal quality as much as for the analog input. the encode inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. each input is biased through a 6k resistor to a 1.6v bias. the bias resistors set the dc oper- ating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. any noise present on the encode signal will result in ad- ditional aperture jitter that will be rms summed with the inherent adc aperture jitter. in applications where jitter is critical (high input frequen- cies), take the following into consideration: 1. differential drive should be used. 2. use as large an amplitude possible. if using trans- former coupling, use a higher turns ratio to increase the amplitude. 3. if the adc is clocked with a ? xed frequency sinusoidal signal, ? lter the encode signal to reduce wideband noise. 4. balance the capacitance and series resistance at both encode inputs such that any coupled noise will appear at both inputs as common mode noise. the encode inputs have a common mode range of 1.2v to v dd . each input may be driven from ground to v dd for single-ended drive. applications information
ltc2207/ltc2206 23 22076fa digital outputs digital output buffers figure 11 shows an equivalent circuit for a single output buffer. each buffer is powered by ov dd and ognd, isolated from the adc power and ground. the additional n-channel transistor in the output driver allows operation down to low voltages. the internal resistor in series with the output eliminates the need for external damping resistors. as with all high speed/high resolution converters, the digi- tal output loading can affect the performance. the digital outputs of the ltc2207/ltc2206 should drive a minimum capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. the output should be buffered with a device such as a alvch16373 cmos latch. for full speed operation the capacitive load should be kept under 10pf. a resistor in series with the output may be used but is not required since the output buffer has a series resistor of 33 on chip. lower ov dd voltages will also help reduce interference from the digital outputs. data format the ltc2207/ltc2206 parallel digital output can be selected for offset binary or 2s complement format. the format is selected with the mode pin. this pin has a four level logic input, centered at 0, 1/3v dd , 2/3v dd and v dd . an external resistor divider can be user to set the 1/3v dd and 2/3v dd logic levels. table 1 shows the logic states for the mode pin. ltc2207/ltc2206 22076 f11 ov dd v dd v dd 0.1 f typical data output ognd ov dd 0.5v to 3.6v predriver logic data from latch 33 ? figure 11. equivalent circuit for a digital output buffer table 1. mode pin function mode output format clock duty cycle stabilizer 0(gnd) offset binary off 1/3v dd offset binary on 2/3v dd 2s complement on v dd 2s complement off over? ow bit an over? ow output bit (of) indicates when the converter is over-ranged or under-ranged. a logic high on the of pin indicates an over? ow or under? ow. output clock the adc has a delayed version of the encode input available as a digital output. both a noninverted version, clkout+ and an inverted version clkoutC are provided. the clkout+/clkoutC can be used to synchronize the con- verter data to the digital system. this is necessary when using a sinusoidal encode. data can be latched on the rising edge of clkout+ or the falling edge of clkoutC. clkout+ falls and clkoutC rises as the data outputs are updated. figure 12. functional equivalent of digital output randomizer clkout + of d15/d0 d14/d0 d2/d0 d1/d0 d0 d0 d1 rand = high, scramble enabled d2 d14 d15 of ltc2207/ltc2206 clkout rand 22076 f12 applications information
ltc2207/ltc2206 24 22076fa applications information digital output randomizer interference from the adc digital outputs is sometimes unavoidable. interference from the digital outputs may be from capacitive or inductive coupling or coupling through the ground plane. even a tiny coupling factor can result in discernible unwanted tones in the adc output spectrum. by randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized, trading a slight increase in the noise ? oor for a large reduction in unwanted tone amplitude. the digital output is randomized by applying an exclu- sive-or logic operation between the lsb and all other data output bits. to decode, the reverse operation is applied; that is, an exclusive-or operation is applied between the lsb and all other bits. the lsb, of and clkout outputs are not affected. the output randomizer function is active when the rand pin is high. output driver power separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. the power supply for the digital output buffers, ov dd , should be tied to the same power supply as for the logic being driven. for example, if the converter is driving a dsp powered by a 1.8v supply, then ov dd should be tied to that same 1.8v supply. in cmos mode ov dd can be powered with any logic voltage up to the v dd of the adc. ognd can be powered with any voltage from ground up to 1v and must be less than ov dd . the logic outputs will swing between ognd and ov dd . internal dither the ltc2207/ltc2206 are 16-bit adcs with a very lin- ear transfer function; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones. small errors in the transfer function are usually a result of adc element mismatches. an optional internal dither mode can be enabled to randomize the input location on the adc transfer curve, resulting in improved sfdr for low signal levels. as shown in figure 15, the output of the sample-and-hold ampli? er is summed with the output of a dither dac. the dither dac is driven by a long sequence pseudo-random number generator; the random number fed to the dither dac is also subtracted from the adc result. if the dither dac is precisely calibrated to the adc, very little of the dither signal will be seen at the output. the dither signal that does leak through will appear as white noise. the dither dac is calibrated to result in less than 0.5db elevation in the noise ? oor of the adc, as compared to the noise ? oor with dither off. figure 13. functional equivalent block diagram of internal dither circuit +? ain ? ain + s/h amp digital summation output drivers multibit deep pseudo-random number generator 16-bit pipelined adc core precision dac clock/duty cycle control clkout of d15 d0 enc dither enable high = dither on low = dither off dith enc analog input 22076 f13 ltc2207/ltc2206
ltc2207/ltc2206 25 22076fa applications information figure 14. descrambling a scrambled digital output d1 d0 d2 d14 d15 ltc2207/ ltc2206 pc board fpga clkout of d15/d0 d14/d0 d2/d0 d1/d0 d0 22076 f14
ltc2207/ltc2206 26 22076fa grounding and bypassing the ltc2207/ltc2206 require a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. the pinout of the ltc2207/ltc2206 has been optimized for a ? owthrough layout so that the interaction between inputs and digital outputs is minimized. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd, v cm , and ov dd pins. bypass capacitors must be located as close to the pins as possible. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the ltc2207/ltc2206 differential inputs should run parallel and close to each other. the input traces should be as short as possible to minimize capacitance and to minimize noise pickup. heat transfer most of the heat generated by the ltc2207/ltc2206 is transferred from the die through the bottom-side exposed pad. for good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the pc board. it is critical that the exposed pad and all ground pins are connected to a ground plane of suf? cient area with as many vias as possible. applications information
ltc2207/ltc2206 27 22076fa top side silkscreen top applications information
ltc2207/ltc2206 28 22076fa inner layer 3 inner layer 2 applications information inner layer 5 inner layer 4
ltc2207/ltc2206 29 22076fa bottom side silkscreen bottom applications information
ltc2207/ltc2206 30 22076fa ordering guide: demo board number part number resolution speed input frequency usb i/f board dc918c-a ltc2207cuk 16-bit 105msps 1mhz to 70mhz dc718 dc918c-b ltc2207cuk 16-bit 105msps 70mhz to 140mhz dc718 dc918c-c ltc2206cuk 16-bit 80msps 1mhz to 70mhz dc718 dc918c-d ltc2206cuk 16-bit 80msps 70mhz to 140mhz dc718 dc918c-e ltc2205cuk 16-bit 65msps 1mhz to 70mhz dc718 dc918c-f ltc2205cuk 16-bit 65msps 70mhz to 140mhz dc718 dc918c-g ltc2204cuk 16-bit 40msps 1mhz to 70mhz dc718 dc918c-h ltc2207cuk-14 14-bit 105msps 1mhz to 70mhz dc718 dc918c-i ltc2207cuk-14 14-bit 105msps 70mhz to 140mhz dc718 dc918c-j ltc2206cuk-14 14-bit 80msps 1mhz to 70mhz dc718 dc918c-k ltc2206cuk-14 14-bit 80msps 70mhz to 140mhz dc718 dc918c-l ltc2205cuk-14 14-bit 65msps 1mhz to 70mhz dc718 see web site for ordering details or contact local sales. applications information
ltc2207/ltc2206 31 22076fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. uk package 48-lead plastic qfn (7mm 7mm) (reference ltc dwg # 05-08-1704) 7.00 0.10 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (wkkd-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (see note 6) pin 1 chamfer 0.40 0.10 48 47 1 2 bottom view?exposed pad 5.15 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uk48) qfn 1103 recommended solder pad pitch and dimensions 0.70 0.05 5.15 0.05 (4 sides) 6.10 0.05 7.50 0.05 0.25 0.05 0.50 bsc package outline package description
ltc2207/ltc2206 32 22076fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2006 lt 0606 rev a ? printed in usa part number description comments ltc1747 12-bit, 80msps adc 72db snr, 87db sfdr, 48-pin tssop package ltc1748 14-bit, 80msps, 5v adc 76.3db snr, 90db sfdr, 48-pin tssop package ltc1749 12-bit, 80msps wideband adc up to 500mhz if undersampling, 87db sfdr ltc1750 14-bit, 80msps, 5v wideband adc up to 500mhz if undersampling, 90db sfdr ltc1993-2 high speed differential op amp 800mhz bw, 70dbc distortion at 70mhz, 6db gain ltc1994 low noise, low distortion fully differential input/output ampli? er/driver low distortion: C94dbc at 1mhz ltc2202 16-bit, 10msps, 3.3v adc, lowest noise 140mw, 81.6db snr, 100db sfdr, 48-pin qfn ltc2203 16-bit, 25msps, 3.3v adc, lowest noise 220mw, 81.6db snr, 100db sfdr, 48-pin qfn ltc2204 16-bit, 40msps, 3.3v adc 480mw, 79db snr, 100db sfdr, 48-pin qfn ltc2205 16-bit, 65msps, 3.3v adc 590mw, 79db snr, 100db sfdr, 48-pin qfn ltc2206 16-bit, 80msps, 3.3v adc 725mw, 77.9db snr, 100db sfdr, 48-pin qfn ltc2207 16-bit, 105msps, 3.3v adc 900mw, 77.9db snr, 100db sfdr, 48-pin qfn ltc2208 16-bit, 130msps, 3.3v adc, lvds outputs 1250mw, 77.7db snr, 100db sfdr, 64-pin qfn ltc2220 12-bit, 170msps adc 890mw, 67.5db snr, 9mm 9mm qfn package ltc2220-1 12-bit, 185msps, 3.3v adc, lvds outputs 910mw, 67.7db snr, 80db sfdr, 64-pin qfn ltc2224 12-bit, 135msps, 3.3v adc, high if sampling 630mw, 67.6db snr, 84db sfdr, 48-pin qfn ltc2249 14-bit, 80msps adc 230mw, 73db snr, 5mm 5mm qfn package ltc2250 10-bit, 105msps adc 320mw, 61.6db snr, 5mm 5mm qfn package ltc2251 10-bit, 125msps adc 395mw, 61.6db snr, 5mm 5mm qfn package ltc2252 12-bit, 105msps adc 320mw, 70.2db snr, 5mm 5mm qfn package ltc2253 12-bit, 125msps adc 395mw, 70.2db snr, 5mm 5mm qfn package ltc2254 14-bit, 105msps adc 320mw, 72.5db snr, 5mm 5mm qfn package ltc2255 14-bit, 125msps, 3v adc, lowest power 395mw, 72.5db snr, 88db sfdr, 32-pin qfn ltc2284 14-bit, dual, 105msps, 3v adc, low crosstalk 540mw, 72.4db snr, 88db sfdr, 64-pin qfn ltc2299 dual 14-bit, 80msps adc 230mw, 71.6db snr, 5mm x 5mm qfn package ltc5512 dc-3ghz high signal level downconverting mixer dc to 3ghz, 21dbm iip3, integrated lo buffer ltc5514 ultralow distortion if ampli? er/adc driver with digitally controlled gain 450 mhz to 1db bw, 47db oip3, digital gain control 10.5db to 33db in 1.5db/step ltc5515 1.5 ghz to 2.5ghz direct conversion quadrature demodulator high iip3: 20dbm at 1.9ghz, integrated lo quadrature generator ltc5516 800mhz to 1.5ghz direct conversion quadrature demodulator high iip3: 21.5dbm at 900mhz, integrated lo quadrature generator ltc5517 40mhz to 900mhz direct conversion quadrature demodulator high iip3: 21dbm at 800mhz, integrated lo quadrature generator ltc5522 600mhz to 2.7ghz high linearity downconverting mixer 4.5v to 5.25v supply, 25dbm iip3 at 900mhz, nf = 12.5db, 50 single-ended rf and lo ports related parts

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